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Interrupt Controller Registers
6.5.1.6 INTC_CONTROL Register (offset = 48h) [reset = 0h]
INTC_CONTROL is shown in Figure 6-9 and described in Table 6-9.
This register contains the new interrupt agreement bits
Figure 6-9. INTC_CONTROL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved NewFIQAgr NewIRQAgr
R-0h W-0h W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-9. INTC_CONTROL Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h Write 0's for future compatibility.
Reads returns 0
1 NewFIQAgr W 0h
Reset FIQ output and enable new FIQ generation
0x0(Write) = nofun_no function effect
0x1(Write) = NewFiq_Reset FIQ output and enable new FIQ
generation
0 NewIRQAgr W 0h
New IRQ generation
0x0(Write) = nofun_no function effect
0x1(Write) = NewIrq_Reset IRQ output and enable new IRQ
generation
211
SPRUH73H–October 2011–Revised April 2013 Interrupts
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