Texas Instruments AM335 Series Technical Reference Manual

Ethernet Subsystem Registers www.ti.com
14.5.2.27 RX_INTSTAT_MASKED Register (offset = A4h) [reset = 0h]
RX_INTSTAT_MASKED is shown in Figure 14-55 and described in Table 14-66.
CPDMA_INT RX INTERRUPT STATUS REGISTER (MASKED VALUE)
Figure 14-55. RX_INTSTAT_MASKED Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
RX7_THRESH_PEND RX6_THRESH_PEND RX5_THRESH_PEND RX4_THRESH_PEND RX3_THRESH_PEND RX2_THRESH_PEND RX1_THRESH_PEND RX0_THRESH_PEND
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RX7_PEND RX6_PEND RX5_PEND RX4_PEND RX3_PEND RX2_PEND RX1_PEND RX0_PEND
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-66. RX_INTSTAT_MASKED Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15 RX7_THRESH_PEND R 0h
RX7_THRESH_PEND masked int read.
14 RX6_THRESH_PEND R 0h
RX6_THRESH_PEND masked int read.
13 RX5_THRESH_PEND R 0h
RX5_THRESH_PEND masked int read.
12 RX4_THRESH_PEND R 0h
RX4_THRESH_PEND masked int read.
11 RX3_THRESH_PEND R 0h
RX3_THRESH_PEND masked int read.
10 RX2_THRESH_PEND R 0h
RX2_THRESH_PEND masked int read.
9 RX1_THRESH_PEND R 0h
RX1_THRESH_PEND masked int read.
8 RX0_THRESH_PEND R 0h
RX0_THRESH_PEND masked int read.
7 RX7_PEND R 0h
RX7_PEND masked int read.
6 RX6_PEND R 0h
RX6_PEND masked int read.
5 RX5_PEND R 0h
RX5_PEND masked int read.
4 RX4_PEND R 0h
RX4_PEND masked int read.
3 RX3_PEND R 0h
RX3_PEND masked int read.
2 RX2_PEND R 0h
RX2_PEND masked int read.
1 RX1_PEND R 0h
RX1_PEND masked int read.
0 RX0_PEND R 0h
RX0_PEND masked int read.
1286
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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Texas Instruments AM335 Series Specifications

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Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English