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Texas Instruments AM335 Series Technical Reference Manual

Texas Instruments AM335 Series
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Integration
13.2.2 LCD Controller Clock and Reset Management
The LCDC module uses the following functional and OCP interface clocks. The L4 Slave interface runs at
half the frequency of the L3 Master interface but uses the same clock. The clock is divided within the
LCDC through the l4_clkdiv input using the pd_per_lcd_l4s_gclk_ien signal from the PRCM. The
functional clock comes from the Display PLL. When the Display PLL is in bypass mode, its output is
sourced by either CORE_CLKOUTM6 or PER_CLKOUTM2.
Table 13-2. LCD Controller Clock Signals
Clock Signal Max Freq Reference / Source Comments
l3_clk 200 MHz CORE_CLKOUTM4 pd_per_lcd_l3_gclk
Master Interface Clock From PRCM
l4_clk 100 MHz CORE_CLKOUTM4 pd_per_lcd_l3_gclk
Slave Interface Clock (divided within LCDC) From PRCM
lcd_clk 200 MHz Display PLL CLKOUT pd_per_lcd_gclk
Functional Clock From PRCM
13.2.3 LCD Controller Pin List
The LCD Controller external interface signals are shown in Table 13-3.
Table 13-3. LCD Controller Pin List
Pin Type Description
lcd_cp O Pixel Clock in Raster model Read Strobe
or Read/Write Strobe in LIDD mode
lcd_pixel_i[15:0] I LCD Data Bus input (for LIDD mode only)
lcd_pixel_o[23:0] O LCD Data Bus output
lcd_lp O Line Clock or HSYNC in Raster mode;
Write Strobe or Direction bit in LIDD mode
lcd_fp O Frame Clock or VSYNC in Raster mode;
Address Latch Enable in LIDD mode
lcd_ac O AC bias or Latch Enable in Raster mode;
Primary Chip Select/Primary Enable in
LIDD MPU/Hitachi mode
lcd_mclk O N/A in Raster mode; Memory
Clock/Secondary chip Select/Secondary
Enable in LIDD Synchronous/Async
MPU/Hitachi mode
1101
SPRUH73HOctober 2011Revised April 2013 LCD Controller
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Texas Instruments AM335 Series Specifications

General IconGeneral
BrandTexas Instruments
ModelAM335 Series
CategoryComputer Hardware
LanguageEnglish

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