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Multimedia Card Registers
18.5.1.27 SD_ADMASAL Register (offset = 258h) [reset = 0h]
SD_ADMASAL is shown in Figure 18-63 and described in Table 18-46.
This register holds the byte address of the executing command of the Descriptor table. The 32-bit Address
Descriptor uses the lower 32 bits of this register. At the start of ADMA, the Host Driver shall set the start
address of the Descriptor table.
Figure 18-63. SD_ADMASAL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADMA_A32B
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-46. SD_ADMASAL Register Field Descriptions
Bit Field Type Reset Description
31-0 ADMA_A32B R/W 0h The ADMA increments this register address, which points to the next
line, whenever fetching a Descriptor line.
When the ADMA Error Interrupt is generated, this register holds the
valid Descriptor address depending on the ADMA state.
The Host Driver shall program the Descriptor Table on a
32-bit boundary and set the
32-bit boundary address to this register.
ADMA2 ignores the lower 2 bits of this register and assumes it to be
00b.
3443
SPRUH73H–October 2011–Revised April 2013 Multimedia Card (MMC)
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