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EDMA3 Registers
11.4.1.6 DMA Channel Registers
The following sets of registers pertain to the 64 DMA channels. The 64 DMA channels consist of a set of
registers (with exception of DMAQNUMn) that each have 64 bits and the bit position of each register
matches the DMA channel number. Each register is named with the format reg_name that corresponds to
DMA channels 0 through 31 and reg_name_High that corresponds to DMA channels 32 through 64.
For example, the event register (ER) corresponds to DMA channel 0 through 31 and the event register
high register (ERH) corresponds to DMA channel 32 through 63. The register is typically called the event
register.
The DMA channel registers are accessible via read/writes to the global address range. They are also
accessible via read/writes to the shadow address range. The read/write ability to the registers in the
shadow region are controlled by the DMA region access registers (DRAEm/DRAEHm). The registers are
described in Section 11.4.1.3.1 and the details for shadow region/global region usage is explained in
EDMA3 Channel Controller Regions.
11.4.1.6.1 Event Registers (ER, ERH)
All external events are captured in the event register (ER/ERH). The events are latched even when the
events are not enabled. If the event bit corresponding to the latched event is enabled
(EER.En/EERH.En = 1), then the event is evaluated by the EDMA3CC logic for an associated transfer
request submission to the transfer controllers. The event register bits are automatically cleared
(ER.En/ERH.En = 0) once the corresponding events are prioritized and serviced. If ER.En/ERH.En are
already set and another event is received on the same channel/event, then the corresponding event is
latched in the event miss register (EMR.En/EMRH.En), provided that the event was enabled
(EER.En/EERH.En = 1).
Event n can be cleared by the CPU writing a 1 to corresponding event bit in the event clear register
(ECR/ECRH). The setting of an event is a higher priority relative to clear operations (via hardware or
software). If set and clear conditions occur concurrently, the set condition wins. If the event was previously
set, then EMR/EMRH would be set because an event is lost. If the event was previously clear, then the
event remains set and is prioritized for submission to the event queues.
The Debug List table provides the type of synchronization events and the EDMA3CC channels associated
to each of these external events.
969
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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