EDMA3 Registers
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The ER is shown in Figure 11-70 and described in Table 11-54. The ERH is shown in Figure 11-71 and
described in Table 11-55.
Figure 11-70. Event Register (ER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 19 E18 E17 E16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-54. Event Register (ER) Field Descriptions
Bit Field Value Description
31-0 En Event 0-31. Events 0-31 are captured by the EDMA3CC and are latched into ER. The events are set
(En = 1) even when events are disabled (En = 0 in the event enable register, EER).
0 EDMA3CC event is not asserted.
1 EDMA3CC event is asserted. Corresponding DMA event is prioritized versus other pending DMA/QDMA
events for submission to the EDMA3TC.
Figure 11-71. Event Register High (ERH)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-55. Event Register High (ERH) Field Descriptions
Bit Field Value Description
31-0 En Event 32-63. Events 32-63 are captured by the EDMA3CC and are latched into ERH. The events are set
(En = 1) even when events are disabled (En = 0 in the event enable register high, EERH).
0 EDMA3CC event is not asserted.
1 EDMA3CC event is asserted. Corresponding DMA event is prioritized versus other pending DMA/QDMA
events for submission to the EDMA3TC.
970
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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