Ethernet Subsystem Registers
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14.5.3.7 CPTS_INTSTAT_MASKED Register (offset = 24h) [reset = 0h]
CPTS_INTSTAT_MASKED is shown in Figure 14-84 and described in Table 14-96.
TIME SYNC INTERRUPT STATUS MASKED REGISTER
Figure 14-84. CPTS_INTSTAT_MASKED Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TS_PEND
R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-96. CPTS_INTSTAT_MASKED Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 TS_PEND R 0h
TS_PEND masked interrupt read (after enable).
1316
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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