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DCAN Registers
23.4.19 INTPND_X Register (offset = ACh) [reset = 0h]
INTPND_X is shown in Figure 23-37 and described in Table 23-32.
With the interrupt pending X register, the CPU can detect if one or more bits in the different interrupt
pending registers are set. Each bit of this register represents a group of eight message objects. If at least
one of the IntPnd bits of these message objects are set, the corresponding bit in the interrupt pending X
register will be set. Example 2. Bit 0 of the interrupt pending X register represents byte 0 of the interrupt
pending 1 register. If one or more bits in this byte are set, bit 0 of the interrupt pending X register will be
set.
Figure 23-37. INTPND_X Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
IntPndReg8 IntPndReg7 IntPndReg6 IntPndReg5
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
IntPndReg4 IntPndReg3 IntPndReg2 IntPndReg1
R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-32. INTPND_X Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15-14 IntPndReg8 R 0h
IntPndReg8
13-12 IntPndReg7 R 0h
IntPndReg7
11-10 IntPndReg6 R 0h
IntPndReg6
9-8 IntPndReg5 R 0h
IntPndReg5
7-6 IntPndReg4 R 0h
IntPndReg4
5-4 IntPndReg3 R 0h
IntPndReg3
3-2 IntPndReg2 R 0h
IntPndReg2
1-0 IntPndReg1 R 0h
IntPndReg1
3945
SPRUH73H–October 2011–Revised April 2013 Controller Area Network (CAN)
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