Multimedia Card Registers
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18.5.1.25 SD_FE Register (offset = 250h) [reset = 0h]
SD_FE is shown in Figure 18-61 and described in Table 18-44.
The Force Event register is not a physically implemented register. Rather, it is an address at which the
Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the
Error Interrupt Status Register, if corresponding bit of the Error Interrupt Status Enable Register is set.
Figure 18-61. SD_FE Register
31 30 29 28 27 26 25 24
Reserved FE_BADA FE_CERR Reserved FE_ADMAE FE_ACE
R-0h W-0h W-0h R-0h W-0h W-0h
23 22 21 20 19 18 17 16
Reserved FE_DEB FE_DCRC FE_DTO FE_CIE FE_CEB FE_CCRC FE_CTO
R-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
FE_CNI Reserved FE_ACIE FE_ACEB FE_ACCE FE_ACTO FE_ACNE
W-0h R-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-44. SD_FE Register Field Descriptions
Bit Field Type Reset Description
31-30 Reserved R 0h
29 FE_BADA W 0h
Force Event Bad access to data space.
0x0 = No effect; no interrupt
0x1 = Interrupt forced.
28 FE_CERR W 0h
Force Event Card error
0x0 = No effect; no interrupt
0x1 = Interrupt forced.
27-26 Reserved R 0h
25 FE_ADMAE W 0h
Force Event ADMA error
0x0 = No effect; no interrupt
0x1 = Interrupt forced.
24 FE_ACE W 0h
Force Event Auto CMD12 error.
0x0 = No effect; no interrupt
0x1 = Interrupt forced.
23 Reserved R 0h
22 FE_DEB W 0h
Force Event Data End Bit error.
0x0 = No effect; no interrupt
0x1 = Interrupt forced.
21 FE_DCRC W 0h
Force Event Data CRC error
0x0 = No effect; no interrupt
0x1 = Interrupt forced.
20 FE_DTO W 0h
Force Event Data timeout error
0x0 = No effect; no interrupt
0x1 = Interrupt forced.
19 FE_CIE W 0h
Force Event Command index error
0x0 = No effect; no interrupt
0x1 = Interrupt forced.
3440
Multimedia Card (MMC) SPRUH73H–October 2011–Revised April 2013
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