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EDMA3 Registers
11.4.2.5.5 Error Interrupt Command Register (ERRCMD)
The error command register (ERRCMD) is shown in Figure 11-113 and described in Table 11-98.
Figure 11-113. Error Interrupt Command Register (ERRCMD)
31 16
Reserved
R-0
15 2 1 0
Reserved Rsvd EVAL
R-0 W-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-98. Error Interrupt Command Register (ERRCMD) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
1 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
0 EVAL Error evaluate
0 No effect
1 EDMA3TC error line is pulsed if any of the error status register (ERRSTAT) bits are set.
1003
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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