CONTROL_MODULE Registers
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9.3.18 init_priority_1 Register (offset = 60Ch) [reset = 0h]
init_priority_1 is shown in Figure 9-21 and described in Table 9-28.
Figure 9-21. init_priority_1 Register
31 30 29 28 27 26 25 24
Reserved debug
R-0h R/W-0h
23 22 21 20 19 18 17 16
lcd sgx Reserved Reserved
R/W-0h R/W-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
usb_qmgr usb_dma Reserved cpsw
R/W-0h R/W-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-28. init_priority_1 Register Field Descriptions
Bit Field Type Reset Description
31-26 Reserved R 0h
25-24 debug R/W 0h Debug Subsystem initiator priority
23-22 lcd R/W 0h LCD initiator priority
21-20 sgx R/W 0h SGX initiator priority
19-18 Reserved R 0h
17-16 Reserved R 0h
15-8 Reserved R 0h
7-6 usb_qmgr R/W 0h USB Queue Manager initiator priority
5-4 usb_dma R/W 0h USB DMA port initiator priority
3-2 Reserved R 0h
1-0 cpsw R/W 0h CPSW initiator priority
780
Control Module SPRUH73H–October 2011–Revised April 2013
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