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Ethernet Subsystem Registers
14.5.5.22 TX5_CP Register (offset = A54h) [reset = 0h]
TX5_CP is shown in Figure 14-110 and described in Table 14-124.
CPDMA_STATERAM TX CHANNEL 5 COMPLETION POINTER REGISTER *
Figure 14-110. TX5_CP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_CP
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-124. TX5_CP Register Field Descriptions
Bit Field Type Reset Description
31-0 TX_CP R/W 0h Tx Completion Pointer Register - This register is written by the host
with the buffer descriptor address for the last buffer processed by the
host during interrupt processing.
The port uses the value written to determine if the interrupt should
be deasserted.
1345
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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