Texas Instruments AM335 Series Technical Reference Manual

www.ti.com I2C Registers
21.4.1.6 I2C_IRQENABLE_SET Register (offset = 2Ch) [reset = 0h]
I2C_IRQENABLE_SET is shown in Figure 21-21 and described in Table 21-14.
All 1-bit fields enable a specific interrupt event to trigger an interrupt request. Writing a 1 to a bit will
enable the field. Writing a 0 will have no effect, that is, the register value will not be modified. For all the
internal fields of the I2C_IRQENABLE_SET register, the descriptions given in the I2C_IRQSTATUS_RAW
subsection are valid.
Figure 21-21. I2C_IRQENABLE_SET Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved XDR_IE RDR_IE Reserved ROVR XUDF AAS_IE BF_IE
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
AERR_IE STC_IE GC_IE XRDY_IE RRDY_IE ARDY_IE NACK_IE AL_IE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-14. I2C_IRQENABLE_SET Register Field Descriptions
Bit Field Type Reset Description
31-15 Reserved R 0h
14 XDR_IE R/W 0h Transmit draining interrupt enable set.
Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR].
0x0 = Transmit draining interrupt disabled
0x1 = Transmit draining interrupt enabled
13 RDR_IE R/W 0h Receive draining interrupt enable set.
Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR].
0x0 = Receive draining interrupt disabled
0x1 = Receive draining interrupt enabled
12 Reserved R 0h
11 ROVR R/W 0h
Receive overrun enable set.
0x0 = Receive overrun interrupt disabled
0x1 = Receive draining interrupt enabled
10 XUDF R/W 0h
Transmit underflow enable set.
0x0 = Transmit underflow interrupt disabled
0x1 = Transmit underflow interrupt enabled
9 AAS_IE R/W 0h Addressed as slave interrupt enable set.
Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS].
0x0 = Addressed as slave interrupt disabled
0x1 = Addressed as slave interrupt enabled
8 BF_IE R/W 0h Bus free interrupt enable set.
Mask or unmask the interrupt signaled by bit in I2C_STAT[BF].
0x0 = Bus free interrupt disabled
0x1 = Bus free interrupt enabled
7 AERR_IE R/W 0h Access error interrupt enable set.
Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR].
0x0 = Access error interrupt disabled
0x1 = Access error interrupt enabled
3729
SPRUH73H–October 2011–Revised April 2013 I2C
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated

Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English