I2C Registers
www.ti.com
Table 21-13. I2C_IRQSTATUS Register Field Descriptions (continued)
Bit Field Type Reset Description
7 AERR R/W 0h
Access Error IRQ enabled status.
0x0 = No action
0x1 = Access error
6 STC R/W 0h
Start Condition IRQ enabled status.
0x0 = No action
0x1 = Start condition detected
5 GC R/W 0h General call IRQ enabled status.
Set to '1' by core when General call address detected and interrupt
signaled to MPUSS.
Write '1' to clear.
0x0 = No general call detected
0x1 = General call address detected
4 XRDY R/W 0h Transmit data ready IRQ enabled status.
Set to '1' by core when transmitter and when new data is requested.
When set to '1' by core, an interrupt is signaled to MPUSS.
Write '1' to clear.
0x0 = Transmission ongoing
0x1 = Transmit data ready
3 RRDY R/W 0h Receive data ready IRQ enabled status.
Set to '1' by core when receiver mode, a new data is able to be read.
When set to '1' by core, an interrupt is signaled to MPUSS.
Write '1' to clear.
0x0 = No data available
0x1 = Receive data available
2 ARDY R/W 0h Register access ready IRQ enabled status.
When set to '1' it indicates that previous access has been performed
and registers are ready to be accessed again.
An interrupt is signaled to MPUSS.
Write '1' to clear.
0x0 = Module busy
0x1 = Access ready
1 NACK R/W 0h No acknowledgment IRQ enabled status.
Bit is set when No Acknowledge has been received, an interrupt is
signaled to MPUSS.
Write '1' to clear this bit.
0x0 = Normal operation
0x1 = Not Acknowledge detected
0 AL R/W 0h Arbitration lost IRQ enabled status.
This bit is automatically set by the hardware when it loses the
Arbitration in master transmit mode, an interrupt is signaled to
MPUSS.
During reads, it always returns 0.
0x0 = Normal operation
0x1 = Arbitration lost detected
3728
I2C SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
