Functional Description
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14.3.1.3.4 Miscellaneous Pulse Interrupt (MISC_PULSE)
The MISC_PULSE interrupt is an immediate, non-paced, pulse interrupt selected from the miscellaneous
interrupts (EVNT_PEND, STAT_PEND, HOST_PEND, MDIO_LINKINT, MDIO_USERINT). The
miscellaneous interrupt(s) is selected by setting one or more bits in the Cn_MISC_EN[4:0] register. The
masked interrupt status can be read in the Cn_MISC_STAT[4:0] register. Upon reception of an interrupt,
software should perform the following:
• Read the Misc_Stat[4:0] register to determine which caused the interrupt.
• Process the interrupt.
• Write the appropriate value (0x3) to the CPDMA_EOI_VECTOR register.
• Write a 1 to the appropriate bit in the MDIOLINKINTRAW register.
14.3.1.3.4.1 EVNT_PEND (CPTS_PEND) Interrupt
See Section 14.3.7, Common Platform Time Sync (CPTS), for information on the time sync event
interrupt.
14.3.1.3.4.2 Statistics Interrupt
The statistics level interrupt (STAT_PEND) will be asserted if enabled when any statistics value is greater
than or equal to 0x80000000. The statistics interrupt is cleared by writing to decrement all statistics values
greater than 0x80000000 (such that their new values are less than 0x80000000). The statistics interrupt is
enabled by setting to one the appropriate bit in the INTMASK_SET register in the CPDMA submodule.
The statistics interrupt is disabled by writing one to the appropriate bit in the INTMASK_CLEAR register.
The raw and masked statistics interrupt status may be read by reading the TX_IntStat_Raw and
TX_IntStat_Masked registers, respectively
14.3.1.3.4.3 Host Error Interrupt
The host error interrupt (HOST_PEND) will be asserted if enabled when a host error is detected during
transmit or receive CPDMA transactions. The host error interrupt is intended for software debug, and is
cleared by a warm reset or a system reset. The raw and masked statistics interrupt status can be read by
reading the TX_INTSTAT_RAW and TXINTSTAT_MASKED registers, respectively.
The following list shows the transmit host error conditions:
• SOP error
• OWNERSHIP bit not set in SOP buffer
• next buffer descriptor pointer without EOP set to 0
• buffer pointer set to 0
• buffer length set to 0
• packet length error
The receive host error conditions are show in the following list:
• Ownership bit not set in input buffer.
• Zero buffer pointer.
• Zero buffer Length on non-SOP descriptor.
• SOP buffer length not greater than offset.
The host error interrupt is disabled by clearing to 0 the appropriate bit in the CPDMA_INTMASK_CLEAR
register.
1180
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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