Functional Description
www.ti.com
19.3.6.1 FIFO Trigger
19.3.6.1.1 Transmit FIFO Trigger
Table 19-14 lists the TX FIFO trigger level settings.
Table 19-14. TX FIFO Trigger Level Setting Summary
UART_SCR[6] UART_TLR[3:0] TX FIFO Trigger Level
0 = 0x0 Defined by the UARTi.UART_FCR[5:4] TX_FIFO_TRIG bit field (8,16, 32, or 56
spaces)
0 != 0x0 Defined by the UARTi.UART_TLR[3:0] TX_FIFO_TRIG_DMA bit field (from 4 to
60 spaces with a granularity of 4 spaces)
1 Value Defined by the concatenated value of TX_FIFO_TRIG_DMA and
TX_FIFO_TRIG (from 1 to 63 spaces with a granularity of 1 space)
Note: The combination of TX_FIFO_TRIG_DMA = 0x0 and TX_FIFO_TRIG =
0x0 (all zeros) is not supported (minimum of one space required). All zeros
result in unpredictable behavior.
19.3.6.1.2 Receive FIFO Trigger
Table 19-15 lists the RX FIFO trigger level settings.
Table 19-15. RX FIFO Trigger Level Setting Summary
UART_SCR[7] UART_TLR[7:4] RX FIFO Trigger Level
0 = 0x0 Defined by the UARTi.UART_FCR[7:6] RX_FIFO_TRIG bit field (8,16, 56, or 60
characters)
0 != 0x0 Defined by the UARTi.UART_TLR[7:4] RX_FIFO_TRIG_DMA bit field (from 4 to
60 characters with a granularity of 4 characters)
1 Value Defined by the concatenated value of RX_FIFO_TRIG_DMA and
RX_FIFO_TRIG (from 1 to 63 characters with a granularity of 1 character)
Note: The combination of RX_FIFO_TRIG_DMA = 0x0 and RX_FIFO_TRIG =
0x0 (all zeros) is not supported (minimum of one character required). All zeros
result in unpredictable behavior.
The receive threshold is programmed using the UARTi.UART_TCR[7:4] RX_FIFO_TRIG_START and
UARTi.UART_TCR[3:0] RX_FIFO_TRIG_HALT bit fields:
• Trigger levels from 0 to 60 bytes are available with a granularity of 4 (trigger level = 4 x [4-bit register
value]).
• To ensure correct device operation, ensure that RX_FIFO_TRIG_HALT RX_FIFO_TRIG when auto-
RTS is enabled.
Delay = [4 + 16 x (1 + CHAR_LENGTH + Parity + Stop 0.5)] x Baud_rate + 4 x FCLK
NOTE: The RTS signal is deasserted after the UART module receives the data over
RX_FIFO_TRIG_HALT. Delay means how long the UART module takes to deassert the RTS
signal after reaching RX_FIFO_TRIG_HALT.
• In FIFO interrupt mode with flow control, ensure that the trigger level to HALT transmission is greater
than or equal to the RX FIFO trigger level (the UARTi.UART_TCR[7:4] RX_FIFO_TRIG_START bit
field or the UARTi.UART_FCR[7:6] RX_FIFO_TRIG bit field); otherwise, FIFO operation stalls. In FIFO
DMA mode with flow control, this concept does not exist, because a DMA request is sent when a byte
is received.
3460
Universal Asynchronous Receiver/Transmitter (UART) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
