Power, Reset, and Clock Management
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8.1.12.2.15 CM_SSC_DELTAMSTEP_DPLL_DDR Register (offset = 38h) [reset = 0h]
CM_SSC_DELTAMSTEP_DPLL_DDR is shown in Figure 8-98 and described in Table 8-106.
Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into
fractional and integer part. [warm reset insensitive]
Figure 8-98. CM_SSC_DELTAMSTEP_DPLL_DDR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved DELTAMSTEP_INTEGER DELTAMSTEP_FRACTION
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
DELTAMSTEP_FRACTION
R/W-0h
7 6 5 4 3 2 1 0
DELTAMSTEP_FRACTION
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-106. CM_SSC_DELTAMSTEP_DPLL_DDR Register Field Descriptions
Bit Field Type Reset Description
31-20 Reserved R 0h
19-18 DELTAMSTEP_INTEGER R/W 0h
Integer part for DeltaM coefficient
17-0 DELTAMSTEP_FRACTIO R/W 0h
Fractional setting for DeltaMStep parameter
N
630
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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