McSPI Registers
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24.4.1.5 McSPI Interrupt Enable Register (MCSPI_IRQENABLE)
This McSPI interrupt enable register (MCSPI_IRQENABLE) enables/disables the module internal sources
of interrupt, on an event-by-event basis. The MCSPI_IRQENABLE is shown in Figure 24-30 and described
in Table 24-15.
Figure 24-30. McSPI Interrupt Enable Register (MCSPI_IRQENABLE)
31 18 17 16
Reserved EOWKE Rsvd
R/W-0 R/W-0 R-0
15 14 13 12 11 10 9 8
Rsvd RX3_FULL_ TX3_UNDERFLOW_ TX3_EMPTY_ Reserved RX2_FULL_ TX2_UNDERFLOW_ TX2_EMPTY_
ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
Rsvd RX1_FULL_ TX1_UNDERFLOW_ TX1_EMPTY_ RX0_OVERFLOW_ RX0_FULL_ TX0_UNDERFLOW_ TX0_EMPTY_
ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 24-15. McSPI Interrupt Enable Register (MCSPI_IRQENABLE) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Reads return 0
17 EOWKE End of word count interrupt enable.
0 Interrupt is disabled.
1 Interrupt is enabled.
16 Reserved Reserved
15 Reserved 0 Reads return 0
14 RX3_FULL_ ENABLE MCSPI_RX3 receiver register full or almost full interrupt enable (channel 3).
0 Interrupt is disabled.
1 Interrupt is enabled.
13 TX3_UNDERFLOW_ ENABLE MCSPI_TX3 transmitter register underflow interrupt enable (channel 3).
0 Interrupt is disabled.
1 Interrupt is enabled.
12 TX3_EMPTY_ ENABLE MCSPI_TX3 transmitter register empty or almost empty interrupt enable
(channel 3).
0 Interrupt is disabled.
1 Interrupt is enabled.
11 Reserved 0 Reads return 0
10 RX2_FULL_ ENABLE MCSPI_RX2 receiver register full or almost full interrupt enable (channel 2).
0 Interrupt is disabled.
1 Interrupt is enabled.
9 TX2_UNDERFLOW_ ENABLE MCSPI_TX2 transmitter register underflow interrupt enable (channel 2).
0 Interrupt is disabled.
1 Interrupt is enabled.
8 TX2_EMPTY_ ENABLE MCSPI_TX2 transmitter register empty or almost empty interrupt enable
(channel 2).
0 Interrupt is disabled.
1 Interrupt is enabled.
7 Reserved 0 Reads return 0
4040
Multichannel Serial Port Interface (McSPI) SPRUH73H–October 2011–Revised April 2013
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