Texas Instruments AM335 Series

www.ti.com McSPI Registers
Table 24-14. McSPI Interrupt Status Register (MCSPI_IRQSTATUS) Field Descriptions (continued)
Bit Field Value Description
2 RX0_FULL Receiver register full or almost full. Channel 0. Receiver register full or almost full. Channel
0
Write 0 Event status bit is unchanged.
Read 0 Event false.
Write 1 Event status bit is reset.
Read 1 Event is pending.
1 TX0_UNDERFLOW Transmitter register underflow. Channel 0.
Write 0 Event status bit is unchanged.
Read 0 Event false.
Write 1 Event status bit is reset.
Read 1 Event is pending.
0 TX0_EMPTY Transmitter register empty or almost empty. Channel 0. This bit indicate FIFO almost full
status when built-in FIFO is use for transmit register (MCSPI_CH3CONF[FFE0W] is set).
Write 0 Event status bit is unchanged.
Read 0 Event false.
Write 1 Event status bit is reset.
Read 1 Event is pending.
4039
SPRUH73H–October 2011–Revised April 2013 Multichannel Serial Port Interface (McSPI)
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated