www.ti.com
Introduction
16.1 Introduction
The USB controller provides a low-cost connectivity solution for numerous consumer portable devices by
providing a mechanism for data transfer between USB devices with a line/bus speed up to 480 Mbps. The
device USB subsystem has two independent USB 2.0 Modules built around two OTG controllers. The
OTG supplement feature, the support for a dynamic role change, is also supported. Each port has the
support for a dual-role feature allowing for additional versatility enabling operation capability as a host or
peripheral. Both ports have identical capabilities and operate independent of each other.
Each USB controller is built around the Mentor USB OTG controller (musbmhdrc) and TI PHY. Each USB
controller has user configurable 32K Bytes of Endpoint FIFO and has the support for 15 ‘Transmit’
endpoints and 15 ‘Receive’ endpoints in addition to Endpoint 0. The USB subsystem makes use of the
CPPI 4.1 DMA for accelerating data movement via a dedicated DMA hardware.
The two USB modules share the CPPI DMA controller and accompanying Queue Manager, Interrupt
Pacer, Power Management module, and PHY/UTMI clock.
Within the descriptions of the USB subsystem that would follow, the term USB controller or USB PHY is
used to mean/refer to any of the two USB controllers or PHYs existing within the USB subsystem. The
term USB module is used to mean/refer to any of the two USB modules. USB0 is used to refer to one of
the USB modules and USB1 is used to refer to the other USB module.
16.1.1 Acronyms, Abbreviations, and Definitions
AHB Advanced High-performance Bus
CBA Common Bus Architecture
CDC Change Data Capture
CPPI Communications Port Programming Interface
CPU Central Processing Unit
DFT Design for Test
DMA Direct Memory Access
DV Design Verification
EOI End of Interrupt
EOP End of Packet
FIFO First-In First-Out
FS Full-Speed USB data rate
HNP Host Negotiation
HS High-Speed USB data rate
INTD Interrupt Distributor
IP Intellectual Property
ISO Isochronous transfer type
LS Low-Speed USB data rate
MHz Megahertz
MOP Middle of Packet
OCP Open Core Protocol
OCP HD OCP High Performance
OCP MMR OCP Memory Mapped Registers
OTG On-The-Go
PDR Physical Design Requirements
PHY Physical Layer Device
PPU Packet Processing Unit
RAM Random Access Memory
RNDIS Remote Network Driver Interface Specification
1691
SPRUH73H–October 2011–Revised April 2013 Universal Serial Bus (USB)
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
