DMTimer
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20.1.5.2 TIOCP_CFG Register (offset = 10h) [reset = 0h]
TIOCP_CFG is shown in Figure 20-10 and described in Table 20-12.
This register allows controlling various parameters of the OCP interface.
Figure 20-10. TIOCP_CFG Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved IDLEMODE EMUFREE SOFTRESET
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-12. TIOCP_CFG Register Field Descriptions
Bit Field Type Reset Description
31-4 Reserved R 0h
3-2 IDLEMODE R/W 0h
Power management, req/ack control
0x0 = Force-idle mode: local target's idle state follows
(acknowledges) the system's idle requests unconditionally, i.e.
regardless of the IP module's internal requirements. Backup mode,
for debug only.
0x1 = No-idle mode: local target never enters idle state. Backup
mode, for debug only.
0x2 = Smart-idle mode: local target's idle state eventually follows
(acknowledges) the system's idle requests, depending on the IP
module's internal requirements. IP module shall not generate (IRQ-
or DMA-request-related) wakeup events.
0x3 = Smart-idle wakeup-capable mode: local target's idle state
eventually follows (acknowledges) the system's idle requests,
depending on the IP module's internal requirements. IP module may
generate (IRQ- or DMA-request-related) wakeup events when in idle
state. Only available for Timer0. Not available for Timer2-7
1 EMUFREE R/W 0h
Emulation mode
0x0 = The timer is frozen in emulation mode (PINSUSPENDN signal
active).
0x1 = The timer runs free, regardless of PINSUSPENDN value.
0 SOFTRESET R/W 0h
Software reset.
0x0x0(W) = No action.
0x0x0(R) = Reset done, no pending action.
0x0x1(W) = Initiate software reset.
0x0x1(R) = Reset ongoing.
3568
Timers SPRUH73H–October 2011–Revised April 2013
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