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GPIO Registers
25.4.1.15 GPIO_CTRL Register (offset = 130h) [reset = 0h]
GPIO_CTRL is shown in Figure 25-21 and described in Table 25-20.
The GPIO_CTRL register controls the clock gating functionality. The DISABLEMODULE bit controls a
clock gating feature at the module level. When set, this bit forces the clock gating for all internal clock
paths. Module internal activity is suspended. System interface is not affected by this bit. System interface
clock gating is controlled with the AUTOIDLE bit in the system configuration register
(GPIO_SYSCONFIG). This bit is to be used for power saving when the module is not used because of the
multiplexing configuration selected at the chip level. This bit has precedence over all other internal
configuration bits.
Figure 25-21. GPIO_CTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved GATINGRATIO DISABLEMODULE
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 25-20. GPIO_CTRL Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2-1 GATINGRATIO R/W 0h Gating Ratio.
Controls the clock gating for the event detection logic.
0x0 = Functional clock is interface clock.
0x1 = Functional clock is interface clock divided by 2.
0x2 = Functional clock is interface clock divided by 4.
0x3 = Functional clock is interface clock divided by 8.
0 DISABLEMODULE R/W 0h
Module Disable
0x0 = Module is enabled, clocks are not gated.
0x1 = Module is disabled, clocks are gated.
4083
SPRUH73H–October 2011–Revised April 2013 General-Purpose Input/Output
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