PORz
nRESETIN_OUT
Internal Chip Resetn
All supplies stable
High frequency system input clock
CLKOUT1 (If SYSBOOT5 = 1)
Duration defined by
PRCM.
PRM_RSTTIME
[7:0]
RSTTIME1
Duration defined by
PRCM.
PRM_RSTTIME [12:8]
RSTTIME2
greater than t
sx
1
Tri-stated with
weak pullup
CLK_M_OSC
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Power, Reset, and Clock Management
GPIO module. GPIO puts all IOs in input mode.
• FuseFarm reset will be de-asserted to start eFuse scanning.
• Once eFuse scanning is complete, reset to the host processor and to all other peripherals (peripherals
without local processor) will be de-asserted.
• nRESETIN_OUT will be de-asserted after time defined by PRM_RSTTIME.RSTTIME1.
• Once host processors finish booting then all remaining peripherals will see reset de-assertion.
Note that all modules with local CPUs will have local reset asserted by default at PORz and reset de-
assertion would require host processor to write to respective registers in PRCM.
Figure 8-19. PORz
(1) For information on t
sx
, see AM335x ARM Cortex-A8 Microprocessors (MPUs) (literature number SPRS717).
8.1.7.3.3 Bad Device Reset
This reset is asserted whenever the DEVICE_TYPE encodes an unsupported device type, such as the
code for a "bad" device.
8.1.7.3.4 Global Cold Software Reset (GLOBAL_COLD_SW_RST)
The source for GLOBAL_COLD_SW_RST is generated internally by the PRM. It is activated upon setting
the PRM_RSTCTRL.RST_GLOBAL_COLD_SW bit in the PRM memory map. This bit is self-clearing, i.e.,
it is automatically cleared by the hardware.
8.1.7.4 Global Warm Reset
8.1.7.4.1 External Warm Reset
nRESETIN_OUT is a bidirectional warm reset signal. As an input, it is typically used by an external source
as a device reset. Refer to Table 8-24 for a summary of the differences between a warm reset and cold
reset. Some of these differences are:
• The warm reset can be blocked to the EMAC switch and its reference clock source PLL using the
RESET_ISO register in the Control Module.
• The warm reset assumes that clocks and power to the chip are stable from assertion through
deassertion, whereas during the cold reset, the power supplies can become stable during assertion
537
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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