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DCAN Registers
23.4.3 ERRC Register (offset = 08h) [reset = 0h]
ERRC is shown in Figure 23-21 and described in Table 23-16.
Figure 23-21. ERRC Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
RP REC[6:0]
R-0h R-0h
7 6 5 4 3 2 1 0
TEC[7:0]
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-16. ERRC Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15 RP R 0h
Receive error passive
0x0 = The receive error counter is below the error passive level.
0x1 = The receive error counter has reached the error passive level
as defined in the CAN specification.
14-8 REC[6:0] R 0h Receive error counter.
Actual state of the receive error counter (values from 0 to 255).
7-0 TEC[7:0] R 0h Transmit error counter.
Actual state of the transmit error counter (values from 0 to 255).
3929
SPRUH73H–October 2011–Revised April 2013 Controller Area Network (CAN)
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