DCAN Registers
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Table 23-15. ES Register Field Descriptions (continued)
Bit Field Type Reset Description
5 EPass R 1h
Error passive state
0x0 = On CAN Bus error, the DCAN could send active error frames.
0x1 = The CAN core is in the error passive state as defined in the
CAN Specification.
4 RxOk R/C 0h Received a message successfully.
This bit will be reset if error and status register is read.
0x0 = No message has been successfully received since the last
time when this bit was read by the CPU. This bit is never reset by
DCAN internal events.
0x1 = A message has been successfully received since the last time
when this bit was reset by a read access of the CPU (independent of
the result of acceptance filtering).
3 TxOk R/C 1h Transmitted a message successfully.
This bit will be reset if error and status register is read.
0x0 = No message has been successfully transmitted since the last
time when this bit was read by the CPU. This bit is never reset by
DCAN internal events.
0x1 = A message has been successfully transmitted (error free and
acknowledged by at least one other node) since the last time when
this bit was reset by a read access of the CPU.
2-0 LEC R/S 7h Last error code.
The LEC field indicates the type of the last error on the CAN bus.
This field will be cleared to '0' when a message has been transferred
(reception or transmission) without error.
0x0 = No error
0x1 = Stuff error. More than five equal bits in a row have been
detected in a part of a received message where this is not allowed.
0x2 = Form error. A fixed format part of a received frame has the
wrong format.
0x3 = Ack error. The message this CAN core transmitted was not
acknowledged by another node.
0x4 = Bit1 error. During the transmission of a message (with the
exception of the arbitration field), the device wanted to send a
recessive level (bit of logical value '1'), but the monitored bus value
was dominant.
0x5 = Bit0 error. During the transmission of a message (or
acknowledge bit, or active error flag, or overload flag), the device
wanted to send a dominant level (logical value '0'), but the monitored
bus level was recessive. During Bus-Off recovery, this status is set
each time a sequence of 11 recessive bits has been monitored. This
enables the CPU to monitor the proceeding of the Bus-Off recovery
sequence (indicating the bus is not stuck at dominant or continuously
disturbed).
0x6 = CRC error. In a received message, the CRC check sum was
incorrect. (CRC received for an incoming message does not match
the calculated CRC for the received data).
0x7 = No CAN bus event was detected since the last time the CPU
read the error and status register. Any read access to the error and
status register re-initializes the LEC to value '7.'
3928
Controller Area Network (CAN) SPRUH73H–October 2011–Revised April 2013
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