Full
Empty
LH or DMA Read
Core Write
.
<MCSPI_IRQSTATUS[TiE]>*
* non-DMA mode only. In DMA mode, the DMA TX request is asserted
to its active level under identical conditions.
<MCSPI_XFERLEVEL[AFL]>
(in bytes)
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Functional Description
24.3.2.10.3 Buffer Almost Empty
The bitfield MCSPI_XFERLEVEL[AEL] is needed when the buffer is used to transmit SPI word to a slave
(MCSPI_CH(I)CONF[FFEW]must be set to 1). It defines the almost empty buffer status.
When FIFO pointer has not reached this level an interrupt or a DMA request is sent to the CPU to enable
system to write AEL+1 bytes to transmit register. Be careful AEL+1 must correspond to a multiple value of
MCSPI_CH(I)CONF[WL].
When DMA is used, the request is de-asserted after the first transmit register write.
No new request will be asserted until the system has performed the correct number of write operations.
Figure 24-20. Buffer Almost Empty Level (AEL)
24.3.2.10.4 End of Transfer Management
When the FIFO buffer is enabled for a channel, the user should configure the MCSPI_XFERLEVEL
register, the AEL and AFL levels, and, especially, the WCNT bit field to define the number of SPI word to
be transferred using the FIFO. This should be done before enabling the channel.
This counter allows the controller to stop the transfer correctly after a defined number of SPI words have
been transferred. If WNCT is cleared to 0, the counter is not used and the user must stop the transfer
manually by disabling the channel, in this case the user doesn’t know how many SPI transfers have been
done. For receive transfer, software shall poll the corresponding FFE bit field and read the Receive
register to empty the FIFO buffer.
When End Of Word count interrupt is generated, the user can disable the channel and poll on
MCSPI_CH(I)STAT[FFE] register to know if SPI word is still there in FIFO buffer and read last words.
4019
SPRUH73H–October 2011–Revised April 2013 Multichannel Serial Port Interface (McSPI)
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