Functional Description
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See Section 8.1.4.6, Functional Sequencing for Power Management with Cortex M3, for specific
information on how the IPC_MSG_REG registers are used to communicate with the Cortex-M3 firmware.
9.2.4.3 Initiator Priority Control
The control module provides the registers to control the bus interconnect priority and the EMIF priority.
9.2.4.3.1 Initiator Priority Control for Interconnect
The INIT_PRIORITY_n register controls the infrastructure priority at the bus interconnects. This can be
used for dynamic priority escalation. There are bit fields that control the interconnect priority for each bus
initiator. By default all the initiators are given equal priority and the allocation is done on a round robin
basis.
The priority can take a value from 0 to 3. The following table gives the valid set of priority values.
Table 9-4. Interconnect Priority Values
Interconnect Priority Value Remarks
00 Low priority
01 Medium priority
10 Reserved
11 High priority
9.2.4.3.2 Initiator Priority at EMIF
The MREQPRIO register provides an interface to change the access priorities for the various masters
accessing the EMIF(DDR). Software can make use of this register to set the requestor priorities for
required EMIF arbitration. The EMIF priority can take a value from 000b to 111b where 000b will be the
highest priority and 111b will be lowest priority.
9.2.4.4 Peripheral Control and Status
9.2.4.4.1 USB Control and Status
The USB_CTRLn and USB_STSn registers reflect the Control and Status of the USB instances. The USB
IO lines can be used as UART TX and RX lines the USB Control register bit field GPIOMODE has settings
that configures the USB lines as GPIO lines. The other USB PHY control settings for controlling the OTG
settings and PHY are part of the USB_CTRLn register.
The USB_STSn register gives the status of the USB PHY module. See the USB_STSn register
description for further details.
See Section 16.2.4, USB GPIO Details, for more information.
9.2.4.4.2 USB Charger Detect
Each USB PHY contains circuitry which can automatically detect the presence of a charger attached to
the USB port. The charger detection circuitry is compliant to the Battery Charging Specification Revision
1.1 from the USB Implementers Forum, which can be found at www.usb.org. See this document for more
details on USB charger implementation.
9.2.4.4.2.1 Features
The charger detection circuitry of each PHY has the following features:
• Contains a state machine which can automatically detect the presence of a Charging Downstream Port
or a Dedicated Charging Port (see the Battery Charging Specification for the definition of these terms)
• Outputs a charger enable signal (3.3 V level active high CMOS driver) when a charger is present.
• Allows you to enable/disable the circuitry to save power
750
Control Module SPRUH73H–October 2011–Revised April 2013
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