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Enhanced Capture (eCAP) Module
15.3.4.1.11 ECCLR Register (offset = 30h) [reset = 0h]
ECCLR is shown in Figure 15-126 and described in Table 15-119.
Figure 15-126. ECCLR Register
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
CMPEQ PRDEQ CNTOVF CEVT4 CEVT3 CEVT2 CEVT1 INT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 15-119. ECCLR Register Field Descriptions
Bit Field Type Reset Description
15-8 Reserved R 0h
7 CMPEQ R/W 0h
Counter Equal Compare Status Flag
0x0 = Writing a 0 has no effect. Always reads back a 0
0x1 = Writing a 1 clears the CMPEQ flag condition
6 PRDEQ R/W 0h
Counter Equal Period Status Flag
0x0 = Writing a 0 has no effect. Always reads back a 0
0x1 = Writing a 1 clears the PRDEQ flag condition
5 CNTOVF R/W 0h
Counter Overflow Status Flag
0x0 = Writing a 0 has no effect. Always reads back a 0
0x1 = Writing a 1 clears the CNTOVF flag condition
4 CEVT4 R/W 0h
Capture Event 4 Status Flag
0x0 = Writing a 0 has no effect. Always reads back a 0.
0x1 = Writing a 1 clears the CEVT3 flag condition.
3 CEVT3 R/W 0h
Capture Event 3 Status Flag
0x0 = Writing a 0 has no effect. Always reads back a 0.
0x1 = Writing a 1 clears the CEVT3 flag condition.
2 CEVT2 R/W 0h
Capture Event 2 Status Flag
0x0 = Writing a 0 has no effect. Always reads back a 0.
0x1 = Writing a 1 clears the CEVT2 flag condition.
1 CEVT1 R/W 0h
Capture Event 1 Status Flag
0x0 = Writing a 0 has no effect. Always reads back a 0.
0x1 = Writing a 1 clears the CEVT1 flag condition.
0 INT R/W 0h
Global Interrupt Clear Flag
0x0 = Writing a 0 has no effect. Always reads back a 0.
0x1 = Writing a 1 clears the INT flag and enable further interrupts to
be generated if any of the event flags are set to 1.
1647
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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