CONTROL_MODULE Registers
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9.3.52 cqdetect_status Register (offset = E00h) [reset = 0h]
cqdetect_status is shown in Figure 9-55 and described in Table 9-62.
Figure 9-55. cqdetect_status Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved cqerr_general cqerr_gemac_b cqerr_gemac_a cqerr_mmcsd_b cqerr_mmcsd_a cqerr_gpmc
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved cqstat_general cqstat_gemac_b cqstat_gemac_a cqstat_mmcsd_b cqstat_mmcsd_a cqstat_gpmc
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-62. cqdetect_status Register Field Descriptions
Bit Field Type Reset Description
31-22 Reserved R 0h
21 Reserved R 0h
20 Reserved R 0h
19 Reserved R 0h
18 Reserved R 0h
17 Reserved R 0h
16 Reserved R 0h
15-14 Reserved R 0h
13 cqerr_general R 0h CQDetect Mode Error Status
12 cqerr_gemac_b R 0h CQDetect Mode Error Status
11 cqerr_gemac_a R 0h CQDetect Mode Error Status
10 cqerr_mmcsd_b R 0h CQDetect Mode Error Status
9 cqerr_mmcsd_a R 0h CQDetect Mode Error Status
8 cqerr_gpmc R 0h CQDetect Mode Error Status
7-6 Reserved R 0h
5 cqstat_general R 0h 1: IOs are 3.3V mode
0: IOs are 1.8V mode
4 cqstat_gemac_b R 0h 1: IOs are 3.3V mode
0: IOs are 1.8V mode
3 cqstat_gemac_a R 0h 1: IOs are 3.3V mode
0: IOs are 1.8V mode
2 cqstat_mmcsd_b R 0h 1: IOs are 3.3V mode
0: IOs are 1.8V mode
1 cqstat_mmcsd_a R 0h 1: IOs are 3.3V mode
0: IOs are 1.8V mode
0 cqstat_gpmc R 0h 1: IOs are 3.3V mode
0: IOs are 1.8V mode
816
Control Module SPRUH73H–October 2011–Revised April 2013
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