WATCHDOG
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CAUTION
If the reload event occurs (after a triggering sequence or after a reset
sequence) before reaching the programmed value (WDT_WDLY[31:0]
WDLY_VALUE), no interrupt is generated.
Also, no interrupt is generated if the value programmed in the delay
configuration register (WDT_WDLY) is less than the value stored in the counter
load register (WDT_WLDR).
20.4.3.12 Watchdog Timers Under Emulation
During emulation mode, the watchdog timer can/cannot continue running, according to the value of the
WDT_WDSC[5] EMUFREE bit of the system configuration register (WDT_WDSC).
• When EMUFREE is 1, watchdog timer execution is not stopped and a reset pulse is still generated
when overflow is reached.
• When EMUFREE is 0, the counters (prescaler/timer) are frozen and incrementation restarts after
exiting from emulation mode.
20.4.3.13 Accessing Watchdog Timer Registers
Posted/nonposted selection applies only to functional registers that require synchronization on/from the
timer functional clock domain (WDTi_FCLK). For write/read operation, the following registers are affected:
• WDT_WCLR
• WDT_WCRR
• WDT_WLDR
• WDT_WTGR
• WDT_WDLY
• WDT_WSPR
The timer interface clock domain synchronous registers are not affected by the posted/nonposted
selection; the write/read operation is effective and acknowledged (command accepted) after one
WDT_ICLK cycle from the command assertion. The timer interface clock domain synchronous registers
are:
• WDT_WIDR
• WDT_WDSC
• WDT_WDST
• WDT_WIRQSTATRAW
• WDT_WIRQSTAT
• WDT_WIRQENSET
• WDT_WIRQENCLR
• WDT_WWPS
3678
Timers SPRUH73H–October 2011–Revised April 2013
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