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20.4.4.1.13 WDT_WIRQSTATRAW Register (offset = 54h) [reset = 0h]
WDT_WIRQSTATRAW is shown in Figure 20-111 and described in Table 20-124.
In the Watchdog Raw Interrupt Status Register, IRQ unmasked status, status set per-event raw interrupt
status vector, line 0. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly
for debug.
Figure 20-111. WDT_WIRQSTATRAW Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved EVENT_DLY EVENT_OVF
R-0h R/W1S-0h R/W1S-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-124. WDT_WIRQSTATRAW Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 EVENT_DLY R/W1S 0h
Settable raw status for delay event
0x0x0(W) = No action
0x0x0(R) = No event pending
0x0x1(W) = Set event (debug)
0x0x1(R) = Event pending
0 EVENT_OVF R/W1S 0h
Settable raw status for overflow event
0x0x0(W) = No action
0x0x0(R) = No event pending
0x0x1(W) = Set event (debug)
0x0x1(R) = Event pending
3694
Timers SPRUH73H–October 2011–Revised April 2013
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