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McASP Registers
22.4.1.46 Read FIFO Control Register (RFIFOCTL)
The Read FIFO control register (RFIFOCTL) is shown in Figure 22-84 and described in Table 22-51.
NOTE: The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO.
If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset.
Figure 22-84. Read FIFO Control Register (RFIFOCTL)
31 17 16
Reserved RENA
R-0 R/W-0
15 8 7 0
RNUMEVT RNUMDMA
R/W-10h R/W-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-51. Read FIFO Control Register (RFIFOCTL) Field Descriptions
Bit Field Value Description
31-17 Reserved 0 Reserved
16 RENA Read FIFO enable bit.
0 Read FIFO is disabled. The RLVL bit in the Read FIFO status register (RFIFOSTS) is reset to 0
and pointers are initialized, that is, the Read FIFO is “flushed.”
1 Read FIFO is enabled. If Read FIFO is to be enabled, it must be enabled prior to taking McASP
out of reset.
15-8 RNUMEVT 0-FFh Read word count per DMA event (32-bit). When the Read FIFO contains at least RNUMEVT
words of data, then an AREVT (receive DMA event) is generated to the host/DMA controller. This
value should be set to a non-zero integer multiple of the number of serializers enabled as
receivers. This value must be set prior to enabling the Read FIFO.
0 0 words
1h 1 word
2h 2 words
3h-40h 3 to 64 words
41h-FFh Reserved
7-0 RNUMDMA 0-FFh Read word count per transfer (32-bit words). Upon a receive DMA event from the McASP, the
Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of
McASP serializers used as receivers. This value must be set prior to enabling the Read FIFO.
0 0 words
1 1 word
2 2 words
3h-10h 3-16 words
11h-FFh Reserved
3879
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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