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I2C Registers
21.4.1.10 I2C_DMATXENABLE_SET Register (offset = 3Ch) [reset = 0h]
I2C_DMATXENABLE_SET is shown in Figure 21-25 and described in Table 21-18.
The 1-bit field enables a transmit DMA request. Writing a 1 to this field will set it to 1. Writing a 0 will have
no effect, that is, the register value is not modified. Note that the I2C_BUF.XDMA_EN field is the global
(slave) DMA enabler, and that it is disabled by default. The I2C_BUF.XDMA_EN field should also be set to
1 to enable a transmit DMA request.
Figure 21-25. I2C_DMATXENABLE_SET Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved DMATX_TRANSMIT_
SET
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-18. I2C_DMATXENABLE_SET Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 DMATX_TRANSMIT_SET R/W 0h
Transmit DMA channel enable set.
3737
SPRUH73H–October 2011–Revised April 2013 I2C
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