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Ethernet Subsystem Registers
14.5.6.43 P2_SA_HI Register (offset = 224h) [reset = 0h]
P2_SA_HI is shown in Figure 14-163 and described in Table 14-178.
CPSW CPGMAC_SL2 SOURCE ADDRESS HIGH REGISTER
Figure 14-163. P2_SA_HI Register
31 30 29 28 27 26 25 24
MACSRCADDR_23_16
R/W-0h
23 22 21 20 19 18 17 16
MACSRCADDR_31_23
R/W-0h
15 14 13 12 11 10 9 8
MACSRCADDR_39_32
R/W-0h
7 6 5 4 3 2 1 0
MACSRCADDR_47_40
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-178. P2_SA_HI Register Field Descriptions
Bit Field Type Reset Description
31-24 MACSRCADDR_23_16 R/W 0h Source Address bits
23:16 (byte 2)
23-16 MACSRCADDR_31_23 R/W 0h Source Address bits
31:23 (byte 3)
15-8 MACSRCADDR_39_32 R/W 0h Source Address bits
39:32 (byte 4)
7-0 MACSRCADDR_47_40 R/W 0h Source Address bits
47:40 (byte 5)
1401
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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