USB Registers
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16.5.4.17 AD_INTERFACE_REG3 Register (offset = 4Ch) [reset = 0h]
AD_INTERFACE_REG3 is shown in Figure 16-150 and described in Table 16-161.
All bits (unless defined) are bypass bits for internal analog to digital interface pins with the same name. All
the bits of this register, except the over-ride bits return a '0' on read, if VDDLDO is off.
Figure 16-150. AD_INTERFACE_REG3 Register
31 30 29 28 27 26 25 24
USE_HSOS_DATA_R HSOS_DATA
EG
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
HSOS_DATA USE_FS_REG3 FSTX_MODE FSTX_SE0 USE_HS_TERM_RES HS_TERM_RES SPARE_IN_LDO
_REG
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
SPARE_IN_LDO SPARE_OUT_LDO
R/W-0h R-0h
7 6 5 4 3 2 1 0
SPARE_OUT_LDO USE_FARCORE_RE FARCORE
G
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-161. AD_INTERFACE_REG3 Register Field Descriptions
Bit Field Type Reset Description
31 USE_HSOS_DATA_REG R/W 0h Use bits
30-23 in this register as bypass bits
30-23 HSOS_DATA R/W 0h
22 USE_FS_REG3 R/W 0h Use bits
20-21 as bypass bits
21 FSTX_MODE R/W 0h
20 FSTX_SE0 R/W 0h
19 USE_HS_TERM_RES_R R/W 0h
Use bit 18 as override bit
EG
18 HS_TERM_RES R/W 0h
17-10 SPARE_IN_LDO R/W 0h
9-2 SPARE_OUT_LDO R 0h
1 USE_FARCORE_REG R/W 0h
Use bit 0 from this register as bypass
0 FARCORE R/W 0h
1924
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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