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I2C Registers
21.4.1.26 I2C_BUFSTAT Register (offset = C0h) [reset = 0h]
I2C_BUFSTAT is shown in Figure 21-41 and described in Table 21-34.
This read-only register reflects the status of the internal buffers for the FIFO management (see the FIFO
Management subsection).
Figure 21-41. I2C_BUFSTAT Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
FIFODEPTH RXSTAT
R-0h R-0h
7 6 5 4 3 2 1 0
Reserved TXSTAT
R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-34. I2C_BUFSTAT Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15-14 FIFODEPTH R 0h Internal FIFO buffers depth.
This read-only bit indicates the internal FIFO buffer depth.
Value after reset is given by the boundary module generic
parameter.
0x0 = 8-bytes FIFO
0x1 = 16-bytes FIFO
0x2 = 32-bytes FIFO
0x3 = 64-bytes FIFO
13-8 RXSTAT R 0h RX buffer status.
This read-only field indicates the number of bytes to be transferred
from the FIFO at the end of the I2C transfer (when RDR is asserted).
It corresponds to the level indication of the RX FIFO (number of
written locations).
Value after reset is 0.
7-6 Reserved R 0h
5-0 TXSTAT R 0h TX buffer status.
This read-only field indicates the number of data bytes still left to be
written in the TX FIFO (it s equal with the initial value of
I2C_CNT.DCOUNT minus the number of data bytes already written
in the TX FIFO through the OCP Interface).
Value after reset is equal with 0.
3761
SPRUH73H–October 2011–Revised April 2013 I2C
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