DCAN Registers
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23.4.34 IF1MSK Register (offset = 104h) [reset = E0000000h]
IF1MSK is shown in Figure 23-52 and described in Table 23-47.
The bits of the IF1 mask registers mirror the mask bits of a message object. While Busy bit of IF1
command register is one, IF1 register set is write protected.
Figure 23-52. IF1MSK Register
31 30 29 28 27 26 25 24
MXtd MDir Reserved Msk[28:0]
R/WP-1h R/WP-1h R-1h R/WP-0h
23 22 21 20 19 18 17 16
Msk[28:0]
R/WP-0h
15 14 13 12 11 10 9 8
Msk[28:0]
R/WP-0h
7 6 5 4 3 2 1 0
Msk[28:0]
R/WP-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-47. IF1MSK Register Field Descriptions
Bit Field Type Reset Description
31 MXtd R/WP 1h Mask Extended Identifier.
When 11 bit (standard) identifiers are used for a message object, the
identifiers of received data frames are written into bits ID28 to ID18.
For acceptance filtering, only these bits together with mask bits
Msk28 to Msk18 are considered.
0x0 = The extended identifier bit (IDE) has no effect on the
acceptance filtering.
0x1 = The extended identifier bit (IDE) is used for acceptance
filtering.
30 MDir R/WP 1h
Mask Message Direction
0x0 = The message direction bit (Dir) has no effect on the
acceptance filtering.
0x1 = The message direction bit (Dir) is used for acceptance filtering.
29 Reserved R 1h
28-0 Msk[28:0] R/WP 0h
Identifier Mask
0x0 = The corresponding bit in the identifier of the message object is
not used for acceptance filtering (don't care).
0x1 = The corresponding bit in the identifier of the message object is
used for acceptance filtering.
3962
Controller Area Network (CAN) SPRUH73H–October 2011–Revised April 2013
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