CONTROL_MODULE Registers
www.ti.com
9.3.60 tpcc_evt_mux_16_19 Register (offset = FA0h) [reset = 0h]
tpcc_evt_mux_16_19 is shown in Figure 9-63 and described in Table 9-70.
Figure 9-63. tpcc_evt_mux_16_19 Register
31 30 29 28 27 26 25 24
Reserved evt_mux_19
R-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved evt_mux_18
R-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved evt_mux_17
R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved evt_mux_16
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-70. tpcc_evt_mux_16_19 Register Field Descriptions
Bit Field Type Reset Description
31-30 Reserved R 0h
29-24 evt_mux_19 R/W 0h Selects 1 of 64 inputs for DMA event 19
23-22 Reserved R 0h
21-16 evt_mux_18 R/W 0h Selects 1 of 64 inputs for DMA event 18
15-14 Reserved R 0h
13-8 evt_mux_17 R/W 0h Selects 1 of 64 inputs for DMA event 17
7-6 Reserved R 0h
5-0 evt_mux_16 R/W 0h Selects 1 of 64 inputs for DMA event 16
824
Control Module SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
