EDMA3 Registers
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11.4.1.1.4 DMA Channel Map n Registers (DCHMAPn)
The DMA channel map n register (DCHMAPn) is shown in Figure 11-45 and described in Table 11-29.
Figure 11-45. DMA Channel Map n Registers (DCHMAPn)
31 16
Reserved
R-0
15 14 13 5 4 0
Reserved PAENTRY Reserved
R-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-29. DMA Channel Map n Registers (DCHMAPn) Field Descriptions
Bit Field Value Description
31-14 Reserved 0 Reserved
13-5 PAENTRY 0-1FFh Points to the PaRAM set number for DMA channel n.
4-0 Reserved 0 Reserved
946
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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