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Touchscreen Controller Registers
12.5.1.53 DMA0REQ Register (offset = ECh) [reset = 0h]
DMA0REQ is shown in Figure 12-57 and described in Table 12-57.
FIFO0 DMA req0 trigger@TSC_ADC_SS_FIFO0 DMA REQUEST Register
Figure 12-57. DMA0REQ Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved DMA_Request_Level
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-57. DMA0REQ Register Field Descriptions
Bit Field Type Reset Description
31-6 Reserved R 0h
RESERVED
5-0 DMA_Request_Level R/W 0h
Number of words in FIFO0 before generating a DMA request
(program to value minus 1)
1091
SPRUH73H–October 2011–Revised April 2013 Touchscreen Controller
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