Ethernet Subsystem Registers
www.ti.com
14.5.1.3 PRESCALE Register (offset = 10h) [reset = 0h]
PRESCALE is shown in Figure 14-17 and described in Table 14-27.
ADDRESS LOOKUP ENGINE PRESCALE REGISTER
Figure 14-17. PRESCALE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PRESCALE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-27. PRESCALE Register Field Descriptions
Bit Field Type Reset Description
19-0 PRESCALE R/W-0 0 ALE Prescale Register - The input clock is divided by this value for
use in the multicast/broadcast rate limiters.
The minimum operating value is 0x10.
The prescaler is off when the value is zero.
1244
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
