DCAN Registers
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23.4.28 MSGVAL78 Register (offset = D0h) [reset = 0h]
MSGVAL78 is shown in Figure 23-46 and described in Table 23-41.
These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the
CPU can check which message objects are valid. The MsgVal bit of a specific message object can be
set/reset by the CPU via the IF1/IF2 interface register sets, or by the message handler after a reception or
a successful transmission.
Figure 23-46. MSGVAL78 Register
31 30 29 28 27 26 25 24
MsgVal[128:113]
R-0h
23 22 21 20 19 18 17 16
MsgVal[128:113]
R-0h
15 14 13 12 11 10 9 8
MsgVal[112:97]
R-0h
7 6 5 4 3 2 1 0
MsgVal[112:97]
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-41. MSGVAL78 Register Field Descriptions
Bit Field Type Reset Description
31-16 MsgVal[128:113] R 0h
Message valid bits (for all message objects)
0x0 = This message object is ignored by the message handler.
0x1 = This message object is configured and will be considered by
the message handler.
15-0 MsgVal[112:97] R 0h
Message valid bits (for all message objects)
0x0 = This message object is ignored by the message handler.
0x1 = This message object is configured and will be considered by
the message handler.
3954
Controller Area Network (CAN) SPRUH73H–October 2011–Revised April 2013
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