McSPI Registers
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24.3.11.3 Main Program
• Interrupt Initialization: (a) Reset status bits in MCSPI_IRQSTATUS (b) Enable interrupts in
MCSPI_IRQENA.
• Channel Configuration: Write MCSPI_CH(i)CONF.
• Start the channel: Write 0000 0001h in MCSPI_CH(i)CTRL.
• First write request: TX empty - Generate DMA write event/ polling TX empty flag by CPU to write First
transmit word into MCSPI_TX(i).
• End of transfer: Stop the channel by writing 0000 0000h in MCSPI_CH(i)CTRL
The end of transfer depends on the transfer mode.
In multi-channel master mode, be careful not to overwrite the bits of other channels when initializing
MCSPI_IRQSTATUS and MCSPI_IRQENABLE.
24.3.12 Interrupt and DMA Events
McSPI has two DMA requests (Rx and Tx) per channel. It also has one interrupt line for all the interrupt
requests.
24.4 McSPI Registers
24.4.1 SPI Registers
Table 24-10 lists the McSPI registers.
Table 24-10. SPI Registers
Offset
Address Acronym Register Name Section
000h MCSPI_REVISION McSPI revision register Section 24.4.1.1
110h MCSPI_SYSCONFIG McSPI system configuration register Section 24.4.1.2
114h MCSPI_SYSSTATUS McSPI system status register Section 24.4.1.3
118h MCSPI_IRQSTATUS McSPI interrupt status register Section 24.4.1.4
11Ch MCSPI_IRQENABLE McSPI interrupt enable register Section 24.4.1.5
124h MCSPI_SYST McSPI system register Section 24.4.1.6
128h MCSPI_MODULCTRL McSPI module control register Section 24.4.1.7
12Ch MCSPI_CH0CONF McSPI channel i configuration register Section 24.4.1.8
130h MCSPI_CH0STAT McSPI channel i status register Section 24.4.1.9
134h MCSPI_CH0CTRL McSPI channel i control register Section 24.4.1.10
138h MCSPI_TX0 McSPI channel i FIFO transmit buffer register Section 24.4.1.11
13Ch MCSPI_RX0 McSPI channel i FIFO receive buffer register Section 24.4.1.12
140h MCSPI_CH1CONF McSPI channel i configuration register Section 24.4.1.8
144h MCSPI_CH1STAT McSPI channel i status register Section 24.4.1.9
148h MCSPI_CH1CTRL McSPI channel i control register Section 24.4.1.10
14Ch MCSPI_TX1 McSPI channel i FIFO transmit buffer register Section 24.4.1.11
150h MCSPI_RX1 McSPI channel i FIFO receive buffer register Section 24.4.1.12
154h MCSPI_CH2CONF McSPI channel i configuration register Section 24.4.1.8
158h MCSPI_CH2STAT McSPI channel i status register Section 24.4.1.9
15Ch MCSPI_CH2CTRL McSPI channel i control register Section 24.4.1.10
160h MCSPI_TX2 McSPI channel i FIFO transmit buffer register Section 24.4.1.11
164h MCSPI_RX2 McSPI channel i FIFO receive buffer register Section 24.4.1.12
168h MCSPI_CH3CONF McSPI channel i configuration register Section 24.4.1.8
16Ch MCSPI_CH3STAT McSPI channel i status register register Section 24.4.1.9
170h MCSPI_CH3CTRL McSPI channel i control register Section 24.4.1.10
4032
Multichannel Serial Port Interface (McSPI) SPRUH73H–October 2011–Revised April 2013
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