Functional Description
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24.3.2 Master Mode
McSPI is in master mode when the bit MS of the register MCSPI_MODULCTRL is cleared.
In master mode McSPI supports multi-channel communication with up to 4 independent SPI
communication channel contexts. McSPI initiates a data transfer on the data lines (SPIDAT [1;0]) and
generates clock (SPICLK) and control signals (SPIEN) to a single SPI slave device at a time.
24.3.2.1 Dedicated Resources Per Channel
In the following sections, the letter “I” indicates the channel number that can be 0, 1, 2 or 3. Each channel
has the following dedicated resources:
• Its own channel enable, programmable with the bit EN of the register MCSPI_CH(I)CTRL. Disabling
the channel, outside data word transmission, remains under user responsibility.
• Its own transmitter register MCSPI_TX on top of the common shift register. If the transmitter register is
empty, the status bit TXS of the register MCSPI_CH(I)STAT is set.
• Its own receiver register MCSPI_RX on top of the common shift register. If the receiver register is full,
the status bit RXS of the register MCSPI_CH(I)STAT is set.
• A fixed SPI ENABLE line allocation (SPIEN[i] port for channel “I”), SPI enable management is optional.
• Its own communication configuration with the following parameters via the register (I)CONF
– Transmit/Receive modes, programmable with the bit TRM.
– Interface mode (Two data pins or Single data pin) and data pins assignment, both programmable
with the bits IS and DPE.
– SPI word length, programmable with the bits WL.
– SPIEN polarity, programmable with the bit EPOL.
– SPIEN kept active between words, programmable with the bit FORCE.
– Turbo mode, programmable with the bit TURBO.
– SPICLK frequency, programmable with the bit CLKD, the granularity of clock division can be
changed using CLKG bit, the clock ratio is then concatenated with MCSPI_CHCTRL[EXTCLK]
value.
– SPICLK polarity, programmable with the bit POL
– SPICLK phase, programmable with the bit PHA.
– Start bit polarity, programmable with the bit SBPOL
– Use a FIFO Buffer or not (see the following note), programmable with FFER and FFEW, depending
on transfer mode, (MCSPI_CH(I)CONF[TRM]).
• Two DMA requests events, read and write, to synchronize read/write accesses of the DMA controller
with the activity of McSPI. The DMA requests are enabled with the bits DMAR and DMAW.
• Three interrupts events
Note: When more than one channel has an FIFO enable bit field (FFER or FFEW) set, the FIFO will not
be used on any channel. Software must ensure that only one enabled channel is configured to use the
FIFO buffer.
The transfers will use the latest loaded parameters of the register MCSPI_CH(I)CONF.
The configuration parameters SPIEN polarity, Turbo mode, SPICLK phase and SPICLK polarity can be
loaded in the MCSPI_CH(I)CONF register only when the channel is disabled. The user has the
responsibility to change the other parameters of the MCSPI_CH(I)CONF register when no transfer occurs
on the SPI interface.
4004
Multichannel Serial Port Interface (McSPI) SPRUH73H–October 2011–Revised April 2013
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