Power, Reset, and Clock Management
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8.1.8 Power-Up/Down Sequence
Each power domain has dedicated warm and cold reset.
Warm reset gets asserted each time there is any warm reset source requesting reset. Warm reset is also asserted when power domain moves
from ON to OFF state.
Cold reset for the domain is asserted in response to cold reset sources. When domain moves from OFF to ON state then also cold reset gets
asserted as this is similar to power-up condition for that domain.
8.1.9 IO State
All IOs except for JTAG i/f and Reset output (and any special cases mentioned in pinlist) should have their output drivers tri-state and internal pulls
enabled during assertion of all reset sources. JTAG i/f IO is affected only by TRSTz.
Note: The PRUs and Cortex M3 processor are held under reset after global warm reset by assertion of software source of reset. Other domains
are held under reset after global warm reset until the MPU software enables their respective interface clock.
8.1.10 Voltage and Power Domains
The following table shows how the device core logic is partitioned into two core logic voltage domains and four power domains. The table lists
which voltage and power domain a functional module belongs.
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Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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