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USB Registers
16.5.5.3 DMAEMU Register (offset = 8h) [reset = 0h]
DMAEMU is shown in Figure 16-154 and described in Table 16-166.
Figure 16-154. DMAEMU Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved SOFT FREE
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-166. DMAEMU Register Field Descriptions
Bit Field Type Reset Description
1 SOFT R/W 0h Control for emulation pause request
1 = Does not force emu_pause_req low
0 = Forces emu_pause_req low
0 FREE R/W 0h
Enable for emulation suspend CPPI DMA Emulation Control Register
1931
SPRUH73H–October 2011–Revised April 2013 Universal Serial Bus (USB)
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