timer_clock
pi_eventcapt
eventcapt_resync
capt_pulse
tcar2_enable
TCRR
FSM State
TCAR2
clear_trig
int_serve
NEW_VALUE NEW_VALUE
LOCKED2 LOCKED2
TCAR1
tcar1_enable
NEW_VALUE NEW_VALUE
Capture Ignored Capture Ignored
UN-LOCKED LOCKED1 UN-LOCKED LOCKED1
pi_eventcapt
eventcapt_resync
capt_pulse
tcar1_enable
TCRR
FSM State
TCAR1
clear_trig
int_serve
TCAR2
timer_clock
UN-LOCKED
LOCKED1
UN-LOCKED
LOCKED1
UN-LOCKED
NEW_VALUE NEW_VALUE NEW_VALUE
Capture Ignored Capture Ignored
DMTimer 1ms
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Figure 20-30. Capture Wave Example for CAPT_MODE 0
In the following example, the TCM value is “01” and CAPT_MODE is “1”- only rising edge of the
PIEVENTCAPT will trigger a capture in TCAR1 on first enabled event and TCAR2 will update on the
second enabled event.
Figure 20-31. Capture Wave Example for CAPT_MODE 1
20.2.3.3 Compare Mode Functionality
When Compare Enable TCLR (CE bit) is set to “1”, the timer value (TCRR) is permanently compared to
the value held in timer match register (TMAR). TMAR value can be loaded at any time (timer counting or
stop). When the TCRR and the TMAR values match, an interrupt can be issued if the TIER (MAT_IT_ENA
bit) is set. The right programming way is to write a compare value in TMAR register before setting TCLR
(CE bit) to avoid any unwanted interrupt due to a reset value matching effect.
3592
Timers SPRUH73H–October 2011–Revised April 2013
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