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Power, Reset, and Clock Management
8.1.13.8.2 PM_CEFUSE_PWRSTST Register (offset = 4h) [reset = 7h]
PM_CEFUSE_PWRSTST is shown in Figure 8-194 and described in Table 8-216.
This register provides a status on the current CEFUSE power domain state. [warm reset insensitive]
Figure 8-194. PM_CEFUSE_PWRSTST Register
31 30 29 28 27 26 25 24
Reserved LastPowerStateEntered
R-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved InTransition Reserved
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LogicStateSt PowerStateSt
R-0h R-1h R-3h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-216. PM_CEFUSE_PWRSTST Register Field Descriptions
Bit Field Type Reset Description
31-26 Reserved R 0h
25-24 LastPowerStateEntered R/W 0h Last low power state entered.
Set to 0x3 upon write of the same only.
This register is intended for debug purpose only.
0x0 = OFF : Power domain was previously OFF
0x1 = ON : Power domain was previously ON-ACTIVE
23-21 Reserved R 0h
20 InTransition R 0h
Domain transition status
0x0 = No : No on-going transition on power domain
0x1 = Ongoing : Power domain transition is in progress.
19-3 Reserved R 0h
2 LogicStateSt R 1h
Logic state status
0x0 = OFF : Logic in domain is OFF
0x1 = ON : Logic in domain is ON
1-0 PowerStateSt R 3h
Current power state status
0x0 = OFF : Power domain is OFF
0x1 = RET : Power domain is in RETENTION
0x2 = INACTIVE : Power domain is ON-INACTIVE
0x3 = ON : Power domain is ON-ACTIVE
745
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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