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Ethernet Subsystem Registers
14.5.2.32 DMA_INTMASK_SET Register (offset = B8h) [reset = 0h]
DMA_INTMASK_SET is shown in Figure 14-60 and described in Table 14-71.
CPDMA_INT DMA INTERRUPT MASK SET REGISTER
Figure 14-60. DMA_INTMASK_SET Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved HOST_ERR_INT_MA STAT_INT_MASK
SK
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-71. DMA_INTMASK_SET Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 HOST_ERR_INT_MASK R/W 0h
Host Error Interrupt Mask - Write one to enable interrupt.
0 STAT_INT_MASK R/W 0h
Statistics Interrupt Mask - Write one to enable interrupt.
1291
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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