WATCHDOG
www.ti.com
Table 20-105 lists the default reset periods for the watchdog timers.
Table 20-105. Default Watchdog Timer Reset Periods
Watchdog Timers Clock Source Default Reset Period
WDT 32 kHz 2 s
20.4.3.7 Triggering a Timer Reload
To reload the timer counter and reset the prescaler before reaching overflow, a reload command is
executed by accessing the watchdog timer trigger register (WDT_WTGR) using a specific reload
sequence.
The specific reload sequence is performed whenever the written value on the WDT_WTGR register differs
from its previous value. In this case, reload is executed in the same way as an overflow autoreload, but
without the generation of a reset pulse.
The timer counter is loaded with the value of the watchdog timer load register (the WDT_WLDR[31:0]
TIMER_LOAD bit field), and the prescaler is reset.
20.4.3.8 Start/Stop Sequence for Watchdog Timers (Using the WDT_WSPR Register)
To start and stop a watchdog timer, access must be made through the start/stop register (WDT_WSPR)
using a specific sequence.
To disable the timer, follow this sequence:
1. Write XXXX AAAAh in WDT_WSPR.
2. Poll for posted write to complete using WDT_WWPS.W_PEND_WSPR.
3. Write XXXX 5555h in WDT_WSPR.
4. Poll for posted write to complete using WDT_WWPS.W_PEND_WSPR.
To enable the timer, follow this sequence:
1. Write XXXX BBBBh in WDT_WSPR.
2. Poll for posted write to complete using WDT_WWPS.W_PEND_WSPR.
3. Write XXXX 4444h in WDT_WSPR.
4. Poll for posted write to complete using WDT_WWPS.W_PEND_WSPR.
All other write sequences on the WDT_WSPR register have no effect on the start/stop feature of the
module.
20.4.3.9 Modifying Timer Count/Load Values and Prescaler Setting
To modify the timer counter value (the WDT_WCRR register), prescaler ratio (the WDT_WCLR[4:2] PTV
bit field), delay configuration value (the WDT_WDLY[31:0] DLY_VALUE bit field), or the load value (the
WDT_WLDR[31:0] TIMER_LOAD bit field), the watchdog timer must be disabled by using the start/stop
sequence (the WDT_WSPR register).
After a write access, the load register value and prescaler ratio registers are updated immediately, but
new values are considered only after the next consecutive counter overflow or after a new trigger
command (the WDT_WTGR register).
20.4.3.10 Watchdog Counter Register Access Restriction (WDT_WCRR Register)
A 32-bit shadow register is implemented to read a coherent value of the WDT_WCRR register because
the WDT_WCRR register is directly related to the timer counter value and is updated on the timer clock
(WDT_FCLK). The shadow register is updated by a 16-bit LSB read command.
3676
Timers SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
